Scalable processors in the billion-transistor era: IRAM
Stylianos Perissakis
David Patterson
Thomas Anderson
Krste Asanovic
Neal Cardwell
Richard Fromm
Jason Golbus
Benjamin Gribstad
Kimberly Keeton
Randi Thomas
Noah Treuhaft
Katherine Yelick
IEEE Computer, 1997
DOI: 10.1109/2.612252
Abstract
Members of the University of California, Berkeley, argue that the memory system will be the greatest inhibitor of performance gains in future architectures. Thus, they propose the intelligent RAM or IRAM. This approach greatly increases the on-chip memory capacity by using DRAM technology instead of much less dense SRAM memory cells. The resultant on-chip memory capacity coupled with the high bandwidths available on chip should allow cost-effective vector processors to reach performance levels much higher than those of traditional architectures. Although vector processors require explicit compilation, the authors claim that vector compilation technology is mature (having been used for decades in supercomputers), and furthermore, that future workloads will contain more heavily vectorizable components.