Pacing Branch Parallelism in LLM Serving

Conference on Neural Information Processing Systems (NeurIPS), 2026


Abstract

Recent methods expose intra-request parallelism in LLM outputs, allowing independent branches to decode concurrently. Existing serving systems execute these branches eagerly or under fixed caps. We show that both are brittle: eager admission inflates the shared decode step, degrading co-batched requests in serial stages, while conservative fixed caps forgo the throughput that motivated exposing branches in the first place. We call the excess step latency caused by admitted branches the \emph{branch externality} and show that the safe width depends on batch composition, context lengths, and accumulated slack, all of which change continuously over a workload trace.

We introduce PACE, a per-step admission controller that treats extra branches as opportunistic width, admitted only when the predicted branch externality fits within the batch’s current slack budget. Per-step regulation is practical because branch-level scheduling decouples compute from memory: branches share the request’s prefix KV, so expanding or contracting width requires no memory reclamation. On Qwen3-32B, PACE improves goodput by 1.77x over serving without branch parallelism and by over eager admission while maintaining 99% SLO attainment. Comparable gains (1.72–2.15x) hold on five additional dense and mixture-of-experts models with up to 671B parameters.