How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level?
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2000
Abstract
Current processor architectures are increasingly dominated by data-access bottlenecks in caches, system buses, and main-memory subsystems. This invited hot-topic paper examines whether future solutions should rely primarily on processor architecture, compiler and synthesis technology, or a combination of both. It discusses explicitly parallel architectures, memory-aware compilation, and the interaction between hardware and software techniques for improving memory performance.