Evaluation of Existing Architectures in IRAM Systems
Workshop on Mixing Logic and DRAM (ISCA), 1997
Abstract
IRAM architectures integrate a processor and DRAM main memory on a single chip, providing high memory bandwidth and reduced memory latency. This paper evaluates whether existing processor microarchitectures can exploit those advantages using execution-time analysis and full-system simulation. The results indicate that contemporary simple, superscalar, and out-of-order architectures are unable to turn IRAM’s bandwidth and latency improvements into significant performance gains for the evaluated workloads.