DRAF: A low-power DRAM-based reconfigurable acceleration fabric

Mingyu Gao; Christina Delimitrou; Dimin Niu; Krishna T Malladi; Hongzhong Zheng; Bob Brennan; Christos Kozyrakis

doi:10.1109/MM.2017.50

DRAF: A low-power DRAM-based reconfigurable acceleration fabric

Mingyu Gao Stanford

Christina Delimitrou Stanford

Dimin Niu Samsung

Krishna T Malladi Samsung

Hongzhong Zheng Samsung

Bob Brennan Samsung

Christos Kozyrakis Stanford

IEEE Micro, 2017

DOI: 10.1109/MM.2017.50

Abstract

DRAF uses commodity DRAM technology to implement dense bit-level reconfigurable logic. Its latency-overlapping techniques and support for multiple configuration contexts improve area density by 10x and reduce power consumption by more than 3x compared with conventional FPGAs while retaining useful performance for datacenter and mobile workloads.

Materials

Bibtex

@inproceedings{2017drafalowpowerdrambasedreconfigurableaccelerationfabricieeemicro,
  title = {DRAF: A low-power DRAM-based reconfigurable acceleration fabric},
  author = {Mingyu Gao and Christina Delimitrou and Dimin Niu and Krishna T Malladi and Hongzhong Zheng and Bob Brennan and Christos Kozyrakis},
  booktitle = {IEEE Micro},
  year = {2017},
  doi = {10.1109/MM.2017.50},
}

Hi, we are the Stanford MAST team

DRAF: A low-power DRAM-based reconfigurable acceleration fabric

Abstract

Materials

Bibtex